Custom Bus Interfaces:

The Vreelin USB 2.0 Device and Host interface cores use a slave microprocessor bus interface and a single interrupt line. The Avalon bus is implemented for Altera and the OPB bus (soon PLB) is implemented for Xilinx. On customer request, practically any bus can be supported. The same situation is true for the USB firmware supplied with each core. All of the firmware is written in standard "C" and is readily portable to other Microprocessor instruction sets and operating systems or RTOS's.

Cost for a new bus interface and microprocessor/OS/RTOS would be based on time and materials.