AXI Development Wars

Update on AXI:

I have both master and slave interfaces running. 

The master interface is blistering fast, but unstable, I.E. USB operations start to malfunction after 100 mega bytes or so of USB data. I'm working on it. The good news is that burst transfers work and can easily keep up with High-Speed USB traffic demands. 

The slave interface is stable, but under Microblaze there are no burst transfers in uncached address space. The only obvious place to put USB on AXI as a slave is AXI "Lite". In typical Xilinx EDK fashion, the AXI Lite bus is dog slow - not useful for USB performance applications. AXI is supposed to synthesize to a cross bar connection with minimal logic (read no delays to speak of) when the clocks are all synchronous and the same speed. All I can tell you is that under EDK 13.1 and the SP605 board, I get a thundering 13 megabytes / sec. This is compared to 52 megabytes /sec on LMB, the forbidden bus that we all use when we need performance. 




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