We fixed the FPGA code generation and now have both host and device cores for USB 2 High Speed on AXI for the Xilinx EDK. Each core has both bus master and slave interfaces allowing USB bus saturation level performance, I.E., 52 megabytes/sec sustained performance.
Both cores have enhanced and configurable queueing support to provide optimized performance while using minimal resources.
Since both cores are coded in System C (C++) and synthesized using the Forte Design Automation Cynthesizer product, we can easily customized each core to meet customer needs. Turn around time can be measured in days, not weeks or months. If you are a high level modeler, then we will supply System C source, if you are an RTL designer, then we supply Verilog RTL or a netlist. And, since this is high level EDA, porting from Xilinx to Altera (when they support AXI) or an ASIC flow is easy. Essentially, there are no core IP changes to move the core from flow to flow. The test bench stays the same, the core coding stays the same.
Because of the dramatic changes that System C brings to the design process, we have formed a new company, HighIP Design, to produce and sell these cores. Please visit http://www.highipdesign.com for more information.