Found the right formula. It was the MPD file for my new usb core. I can now achieve 52 megabytes/sec (USB saturation speed) using AXI DMA to/from the DDR memory on AXI. As usual with Microblaze and DD anything memory, the cache size is very important. If you use the default of 8KB for data and instruction cache, then 4 buffers per endpoint in the new core architecture are required. If you increase the Microblaze cache to 16KB data and instruction, then the USB core can use 2 buffers per endpoint. Each bram will hold 8 buffers so keeping the Microblaze cache small and adding core buffers may be the better option. More later as I have a chance to play with the various sizes.