Using the Forte Cynthesizer compiler, we are able to get hand coded verilog performance while coding the core in System C (C++). This is a big productivity boost for everyone. Current ASIC results taking the verilog output of Cynthesizer, and running it through Design Compiler for a TSMC .18 micron process are excellent - almost the same as hand coded. FPGA results are not, yet, but this is a compiler problem and will get fixed. The advantages are huge. The entire AXI interface, including high performance DMA is in one .h file. It's a class, so every time you need AXI, there is no more typing 40 signal names, you just instantiate the class, I.E., axi::master, axi::slave, axi::bus.
System C makes the core much easier to modify and keeps the design process invariant. Moving from software to hardware is much easier since the target language is C++.
For none Forte Cynthesizer customers, we will build RTL in verilog for you. In all cases, the System C model will be available for simulation use.
The website design is almost complete, it won't be long now.
Other news, I'm coding superspeed USB in System C. About 50% done.