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Vreelin Engineering High Speed USB 2.0 Device I/F Core For Xilinx FPGA's

Xilinx ML403 Development Board with SMSC 3300PHY Daughter Card Implementing Vreelin USB 2.0 High Speed Device Interface

Block Diagram of the USB 2.0 Device Core

Description:

Vreelin's USB 2.0 device core for Xilinx FPGA's integrates into the Xilinx Embedded Development kit. A Developer can quickly and easily add a USB 2.0 interface into an EDK project. The Vreelin USB 2.0 device core has a small footprint of 750 Slices on a Virex4 FPGA and uses a ULPI compliant external PHY that requires only 12 pins. The core attaches to the Xilinx OPB bus as a slave device and appears as RAM plus a small number of hardware registers. Pushbutton system configuration with Platform Studio allows the developer to add, delete or modify the core under the Platform Studio environment. Multiple cores can be added to a design as needed. The core supports both the PPC and Microblaze processors and runs on Spartan 3, Virtex 2, Virtex 2Pro, and Virtex4 FPGA's. Fully plug and play compliant, the Vreelin USB 2.0 core includes working USB Chapter 9 firmware and Win2K/XP device driver software which can be customized by the developer for specific application needs.  The device driver supplies W32API ReadFile and WriteFile for data, and DeviceIoControl calls for control. Multiple handles can be opened to the device driver so that the developer's Windows application can be implemented in multiple program contexts

Versital and configurable, Vreelin's USB 2.0 device core supplies control endpoint 0 plus 7 end points for the developer's application. Double buffering is provided for each end point. The maximum packet size for Bulk and Interrupt endpoints is 512 bytes. ISO endpoints can be 1024 bytes. Each endpoint's type (bulk, interrupt, or ISO), max packet size, and buffer location in dual port RAM is configured by the firmware.  Up to 16 KB of Block RAM can be allocated as needed to meet endpont buffering needs. As supplied, the Vreelin's USB 2.0 device core uses 4 Block RAM's or 8KB. HDL source code for the dual port RAM module is provided to allow the developer to minimize the memory foot print. To meet special circumstances, the core can be custom built by Vreelin Eng. with more or less than 8 endpoints and with other special features as required such as custom hardware interfaces for specific endpoints. The core sustains USB 2.0 high speed transfer rates up to the limits of the USB bus and is certified USB 2.0 Logo Compliant.

• Supports Power PC and Microblaze Processors
• Efficient Small Size: 750 Slices on a Virtex 4
• High performance - 9 megabytes/sec  when used with the Vreelin Windows XP device driver
• Vreelin HWIF port increases performance to 44 megabytes/sec
• Attaches to OPB bus as a slave device looks like RAM
• Uses Block Ram for Data Buffering
• Supports external ULPI compliant PHY (12 pin I/F)
• Works seamlessly with the SMSC 3300 PHY
• Seamless Integration into the Xilinx Embedded Development Kit
• Can be added to a Platform Studio project like any other core from Xilinx
• Complete firmware for USB Chapter 9 Processing and example application code
• Working plug and play device driver for Microsoft Win2K/ Win XP  - others developed on a custom basis
• Flexible and Configurable - Supports up to 7 application endpoints All 7endpoints are configurable as bulk, interrupt, or ISO. All endpoints have double buffering.

To Request an Evaluation:

Contact salesATvreelin.com

A signed NDA is required for the evaluation due to the firmware source code provided.

Downloads:

• Download User Manaul
• Download Core template
• Download Dual Port RAM Template
• Download Data Sheet in PDF

Basic Pricing:

Net List: $15,000 per project
Includes:

• USB 2.0 Core (encrypted source )
• firmware driver including clear text source code
• Sample firmware application (including source code)
• Windows device driver (including source code)
• Installation scripts for the Windows device driver
• Sample windows console application (including source code) that uses the Windows device driver to communicate with the core over USB.
• Documentation

Location Site License : $50,000.00

• Site wide net list license at one company location for any number of projects.

HDL Source Code License: $100,000.00
Adds:

• Complete source code including clear text HDL
• Test Bench for HDL
• Location site license for any number of projects

Standard Yearly Service Contract:

• up to 20 hours of support  plus bug fixes and minor enhancements - 20% of license

Hourly Contract for Customization:

• billed at $200/hour

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